1. Field of the Invention
The embodiments relate to integrated circuits and, more specifically, to an integrated circuit structure incorporating a conductor layer, such as a redistribution layer, with both top surface and sidewall passivation and a method of forming the integrated circuit structure.
2. Description of the Related Art
During back end of the line (BEOL) processing of integrated circuit structures, redistribution layers may be formed to provide low resistance, on-chip interconnects. Such redistribution layers may also be formed to allow integrated circuit structures, which were originally designed for wirebonding, to be used in flip-chip packages. Unfortunately, current low-cost processing techniques for forming redistribution layers suffer from poor dimensional control due to insufficient sidewall passivation. Poor dimensional control, in turn, results in reduced reliability, particularly with continued size-scaling of integrated circuit structures. Therefore, there is a need in the art for a method of forming an integrated circuit structure that incorporates a redistribution layer with both top surface and sidewall passivation to ensure greater dimensional control and, thereby greater reliability.